1. Field of the Invention
This invention relates to integrated circuit fabrication and, more particularly, to a method for fabricating a transistor having ultrathin nitrogen-containing sidewall spacers.
2. Description of the Related Art
Fabrication of a metal-oxide-semiconductor (MOS) integrated circuit involves numerous processing steps. Typically, a gate dielectric is formed on a semiconductor substrate which is doped with either n-type or p-type impurities. For each MOS field effect transistor (MOSFET) being formed, a gate conductor is formed over the gate dielectric, and dopant impurities are introduced into the substrate to form a source and drain. Dielectric spacers are often formed on the sidewalls of the gate conductor and used to form lightly-doped drain (LDD) portions of the source and drain. According to the conventional method of forming these LDD regions, the above-mentioned dopant impurities are introduced in two steps. A first impurity introduction is performed after gate conductor formation to form impurity distributions self-aligned to sidewalls of the gate conductor. A conformal dielectric layer, typically a silicon dioxide ("oxide") layer is subsequently blanket deposited over the semiconductor substrate and gate conductor. This oxide layer is anisotropically etched more rapidly in a vertical than a horizontal direction, so that oxide spacers are formed adjacent to the gate conductor sidewalls. A second impurity introduction is subsequently performed to form impurity distributions self aligned to lateral surfaces of the spacers. The impurity distributions formed by the second impurity introduction have higher carrier concentration and extend farther into the substrate than those formed by the first impurity introduction.
The impurity distributions formed by the first and second impurity introductions combine to form source and drain regions which include relatively lightly-doped portions, or LDD regions, underneath the sidewall spacers. Such LDD regions reduce the maximum electric field at the drain/channel interface in a MOSFET. The reduction in electric field lowers the kinetic energy gained by electrons in the MOSFET channel, thereby mitigating undesirable "hot-carrier" effects. Hot-carrier effects include avalanche breakdown at the drain/substrate junction and injection of carriers into the gate dielectric.
The alleviation of hot-carrier effects provided by the LDD regions does come at a price, however. The lightly-doped LDD regions have greater resistivity than more heavily doped portions of the source and drain, and therefore act to increase the series resistance encountered by electrons or holes traveling from the source to the drain. This increased resistance lowers the saturated drain current I.sub.dsat of the MOSFET, which in turn lowers the speed of the device. It is therefore believed to be important to make LDD region widths no larger than needed to achieve an acceptable level of electric field reduction. Since the lateral width of an LDD region is substantially determined by the width of the overlying spacer, spacer widths should be controlled. In particular, as overall dimensions of transistors continue to shrink, the lateral widths of sidewall spacers must decrease as well. Because MOSFET gate conductor widths are currently approaching 0.1 micron, sidewall spacer widths may comprise a significant portion of the path length between the source and drain unless spacers having thicknesses of less than about 500 angstroms can be fabricated. Although this reduction in MOSFET gate conductor width, and therefore a reduction in channel length, might be expected to result in increased electric fields in transistors, operating voltages for many devices have been decreasing as well, which opposes the effect of a shortened channel on maximum electric field. It is therefore believed that transistor performance can be enhanced using narrow spacers.
In addition to the increased series resistance which may result if spacers are made excessively wide, transistor reliability problems may be associated with sidewall spacers. As noted above, spacers are typically formed from a deposited oxide layer. Some of the dopant impurities used in transistor fabrication diffuse readily through oxide. In particular, boron is known to exhibit significant outdiffusion from silicon into overlying oxide layers during MOSFET fabrication. In a p-channel transistor, for example, boron may diffuse from the p-type source and drain into oxide sidewall spacers. This outdiffusion of boron from the substrate lowers the carrier concentration of the source and drain regions, thereby increasing series and contact resistances associated with the source and drain.
Another reliability problem which may be associated with oxide spacers is "bridging" over spacers during self-aligned silicide, or salicide, processes. Salicide processes are performed in order to provide relatively broad-area, low-resistivity (and therefore low-resistance) contacts to the source, drain, and gate of a transistor. In a salicide process, a metal film is blanket-deposited over the exposed surfaces of a transistor containing sidewall spacers, after formation of the source and drain regions. The transistor is subjected to a heating process which causes a reaction between the metal and silicon that the metal is in contact with, forming a silicide on the silicon surfaces. Unreacted metal is subsequently removed, leaving the silicide covering only the gate, source, and drain regions. In some cases, however, a silicide connection, or "bridging", can occur across oxide sidewall spacers between the gate and source or drain regions. Bridging can occur when silicon atoms from the gate, source and or drain regions diffuse into the metal overlying the sidewall spacers, so that a silicide is formed on the spacers. Titanium is a popular silicide metal because it has a very low resistance. Unfortunately, titanium salicide processes are particularly prone to bridging. The formation of ultrathin oxide spacers may further exacerbate this problem by reducing the distance between the gate and source or drain silicide regions.
It would be advantageous to develop ultrathin (less than about 500 angstroms wide) spacers to improve series resistance and saturated drain current of MOSFETs. The continual shrinking of transistor dimensions results in reduced tolerances for these dimensions. In other words, it is becoming increasingly important that device dimensions change as little as possible during the course of a fabrication process. This suggests an increased importance for low-temperature processing, so that diffusion of dopants and other atoms from their intended positions is minimized.
It would therefore be desirable to develop a process to form ultrathin MOSFET sidewall spacers. These spacers should minimize reliability problems associated with many typical oxide spacers, such as dopant diffusion and salicide bridging. Furthermore, the spacers should be fabricated using a low-temperature process, so that diffusion in the underlying transistor is minimized.